Input buffer with voltage clamping for compatibility

An input/output buffer is provided with input buffer circuitry which can be used to make an integrated circuit selectively compatible with one of a number of interface types, such as PCI, GTL, PECL, ECL and SSTI. The input buffer portion includes a CMOS transistors for driving the output (OUT) betwe...

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Bibliographic Details
Main Author SHARPE-GEISLER BRADLEY A
Format Patent
LanguageEnglish
Published 30.03.2004
Edition7
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Summary:An input/output buffer is provided with input buffer circuitry which can be used to make an integrated circuit selectively compatible with one of a number of interface types, such as PCI, GTL, PECL, ECL and SSTI. The input buffer portion includes a CMOS transistors for driving the output (OUT) between the VSS and VDD rails similar to CMOS logic. The voltage and current on the output of the input buffer as controlled by the CMOS transistors is clamped to levels depending on a mode select signal applied to selectively provide different output levels compatible with PCI, GTL, PECL, ECL and SSTI signals.
Bibliography:Application Number: US20020146739