Memory-to-memory copy and compare/exchange instructions to support non-blocking synchronization schemes
A coherency technique for multiprocessor systems in which threads perform atomic read or atomic write transactions pursuant to memory-to-memory copy instructions or memory-to-memory compare-and-exchange instructions. Although the source reads and target writes are each atomic, the instruction is not...
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Main Author | |
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Format | Patent |
Language | English |
Published |
16.03.2004
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Edition | 7 |
Subjects | |
Online Access | Get full text |
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