Memory-to-memory copy and compare/exchange instructions to support non-blocking synchronization schemes

• Main Author: ZAHIR ACHMED RUMI
• Format: Patent
• Language: English
• Published: 16.03.2004
• Edition: 7
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

A coherency technique for multiprocessor systems in which threads perform atomic read or atomic write transactions pursuant to memory-to-memory copy instructions or memory-to-memory compare-and-exchange instructions. Although the source reads and target writes are each atomic, the instruction is not required to be atomic from the read through the write operation. Accordingly, once a first thread reads source data pursuant to a read, for example, it may allow other threads to access that data prior to completing its own target write. The data may include a version stamp. After the first thread operates on the data, software may read in the version stamp a second time. If the two version stamps agree, the results of the thread's operation may be considered valid for lookup operations. For a compare and exchange operation, a thread may read data from a source location. Subsequently, the thread may read atomically a current copy of a version stamp from a target address, compare it to a version of the same version stamp obtained earlier, and, if the two version stamps agree, write the source data to the target address.