Field effect transistor and method of fabricating the same by controlling distribution condition of impurity region with implantation of additional ion

• Main Authors: HORIUCHI MASATADA, TAKAHAMA TAKASHI
• Format: Patent
• Language: English
• Published: 10.02.2004
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A first object of the present invention is to provide an insulated gate field effect transistor which realizes reductions in the junction depth and the resistance of source and drain junction regions beneath a gate electrode. Another object is to provide a miniaturized complementary type insulated gate field effect transistor capable of achieving a large current and a high operation speed. In a miniaturized MOS transistor, a low concentration impurity integrated layer comprising In or Ga is provided so as to have a peak in the inside of high concentration shallow source and drain diffusion layer regions. By this arrangement, the shallow source and drain diffusion layers are attracted by the impurity integrated layer, to realize shallower junctions having a high concentration and a rectangular distribution. As a result, particularly, a miniaturized PMOS with a larger current, punch-through hard and an ultra miniaturized configuration is achieved, and this can be applied also to NMOS, and, therefore, a CMOS with a larger current, punch-through hard and a more miniaturized configuration can be achieved without complicating the fabrication steps, namely, economically.