Method to combine zero-etch and STI-etch processes into one process

• Main Authors: PENG JOHNSON, SUN ERIC, SU BIN-JIA, CHEN JACKY
• Format: Patent
• Language: English
• Published: 23.12.2003
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A method for integrating the zero-etch and STI-etch processes into one process is described. An etch stop layer is deposited on a substrate. A mask is formed overlying the etch stop layer having a first opening for a planned alignment mark and having a second opening for a planned shallow trench isolation region. The etch stop layer is etched away within the first and second openings and the semiconductor substrate exposed within the first and second openings is etched into a first depth to form a first trench underlying the first opening and a second trench underlying the second opening. The first trench is covered and the second trench is etched into the semiconductor substrate to a second depth greater than the first depth. The second trench is filled to complete formation of a shallow trench isolation region wherein the first trench completes formation of an alignment mark in the fabrication of an integrated circuit device.