Data transfer with highly granular cacheability control between memory and a scratchpad area

• Main Authors: FALARDEAU BRIAN D, NORROD FORREST E, BRIGGS WILLARD S, WILCOX CHRISTOPHER G
• Format: Patent
• Language: English
• Published: 22.07.2003
• Edition: 7
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

A processing system having a CPU core and a cache transfers data between a first block of memory and a second block of memory that is preferably partitioned out of the cache as a non-cacheable scratchpad area and performs address calculations with protection and privilege checks without polluting th...