Data transfer with highly granular cacheability control between memory and a scratchpad area

A processing system having a CPU core and a cache transfers data between a first block of memory and a second block of memory that is preferably partitioned out of the cache as a non-cacheable scratchpad area and performs address calculations with protection and privilege checks without polluting th...

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Bibliographic Details
Main Authors FALARDEAU BRIAN D, NORROD FORREST E, BRIGGS WILLARD S, WILCOX CHRISTOPHER G
Format Patent
LanguageEnglish
Published 22.07.2003
Edition7
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A processing system having a CPU core and a cache transfers data between a first block of memory and a second block of memory that is preferably partitioned out of the cache as a non-cacheable scratchpad area and performs address calculations with protection and privilege checks without polluting the cache. Responsive to executing a predetermined instruction, the CPU core signals the cache to prevent caching data during transfer from system to scratchpad memory thereby reducing the number of bus turnarounds while maintaining byte granularity addressability.
Bibliography:Application Number: US19970950513