Dual gate oxide process without critical resist and without N2 implant

A process as shown in FIGS. 1A through 1I, or FIGS. 2A through 2I for providing first areas of gate oxide (30, 30A, 30B) on a substrate (10) having a first thickness and second adjacent areas (32, 32A, 32B) of gate oxide having a lesser thickness without the use of a N2 implantation process.

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Bibliographic Details
Main Authors RAMACHANDRAN RAVIKUMAR, TEWS HELMUT H, LEE KILHO
Format Patent
LanguageEnglish
Published 17.06.2003
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A process as shown in FIGS. 1A through 1I, or FIGS. 2A through 2I for providing first areas of gate oxide (30, 30A, 30B) on a substrate (10) having a first thickness and second adjacent areas (32, 32A, 32B) of gate oxide having a lesser thickness without the use of a N2 implantation process.
Bibliography:Application Number: US20020077518