Flip chip package with improved cap design and process for making thereof

Wire bond packages which mount encapsulated semiconductor chips, such as plastic ball grid array (PBGA) packages providing for the mounting of so-called flip-chips. The chips are overlaid with heat spreading perforated cap wherein the perforations are filled with an adhesive to prevent delamination...

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Main Authors FARQUHAR DONALD S, HOUSER DAVID E, PAPATHOMAS KONSTANTINOS I
Format Patent
LanguageEnglish
Published 31.12.2002
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Abstract Wire bond packages which mount encapsulated semiconductor chips, such as plastic ball grid array (PBGA) packages providing for the mounting of so-called flip-chips. The chips are overlaid with heat spreading perforated cap wherein the perforations are filled with an adhesive to prevent delamination caused by mismatches in the coefficients of thermal expansion, resulting in contractions which cause the entire package arrangement to warp, leading to delamination between an encapsulant and cap and resulting in failure of connect joints and the ball grid arrays.
AbstractList Wire bond packages which mount encapsulated semiconductor chips, such as plastic ball grid array (PBGA) packages providing for the mounting of so-called flip-chips. The chips are overlaid with heat spreading perforated cap wherein the perforations are filled with an adhesive to prevent delamination caused by mismatches in the coefficients of thermal expansion, resulting in contractions which cause the entire package arrangement to warp, leading to delamination between an encapsulant and cap and resulting in failure of connect joints and the ball grid arrays.
Author FARQUHAR DONALD S
HOUSER DAVID E
PAPATHOMAS KONSTANTINOS I
Author_xml – fullname: FARQUHAR DONALD S
– fullname: HOUSER DAVID E
– fullname: PAPATHOMAS KONSTANTINOS I
BookMark eNqNjDsKAjEURVNo4W8PbwOCURx7xUFrtR5C5ubDzLyEJOj2TeECbO6Bw-EuxYwDYyHu7egjaVcnKj0oC_r44shPMYU3etIqUo_sLZPinqrVyJlMSDSpwbOl4pAQzFrMjRozNj-uBLXX5-W2RQwdcn0Ho3SvR3PcSXmS5_3hj-QLXtY1sg
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
Edition 7
ExternalDocumentID US6501171B2
GroupedDBID EVB
ID FETCH-epo_espacenet_US6501171B23
IEDL.DBID EVB
IngestDate Fri Jul 19 16:04:55 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_US6501171B23
Notes Application Number: US20010774152
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20021231&DB=EPODOC&CC=US&NR=6501171B2
ParticipantIDs epo_espacenet_US6501171B2
PublicationCentury 2000
PublicationDate 20021231
PublicationDateYYYYMMDD 2002-12-31
PublicationDate_xml – month: 12
  year: 2002
  text: 20021231
  day: 31
PublicationDecade 2000
PublicationYear 2002
RelatedCompanies INTERNATIONAL BUSINESS MACHINES CORPORATION
RelatedCompanies_xml – name: INTERNATIONAL BUSINESS MACHINES CORPORATION
Score 2.5696225
Snippet Wire bond packages which mount encapsulated semiconductor chips, such as plastic ball grid array (PBGA) packages providing for the mounting of so-called...
SourceID epo
SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title Flip chip package with improved cap design and process for making thereof
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20021231&DB=EPODOC&locale=&CC=US&NR=6501171B2
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1bS8MwFD6MKeqbTsV5Iw_St2Jrb_OhCL0xBbfhVtnbaNKEFbUtruLf9ySu0xd9CSGBcBL4zi3nAnBFhc1ZRhFIuWWhgeJSnbq3nu45nmDMZsKgKsp35A5T-2HuzDtQtLkwqk7opyqOiIhiiPdG8ev6x4kVqdjK1TUtcKm6S2Z-pLXWsWTEphYFfjwZR-NQC0M_nWqjJx8VEdP0zAC59ZasuiXL7MfPgUxKqX9LlGQftid4WNkcQIeXPdgN28ZrPdh5XP9343QNvdUh3CevRU3YEgek-AXZAJE-VFIorwDPCctqkqt4DJKVOam_MwAIKqXkTbWcIlLX45U4ApLEs3CoI02Lzf0X6XRDvXUM3bIq-QkQkQmPGhlzuEHRKssHFoo7ceOiBGa2GDh96P95zOk_e2ew13Y8scxz6DbvH_wCBW9DL9WTfQFHwYmJ
link.rule.ids 230,308,780,885,25564,76547
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3NS8MwFH-MKc6bTsX5mYP0Vlzt1zwUoe3Kpls3XCe7jSZNsKhtcRX_fV_jOr3oJYQEwkvg977yPgCuqDA4iykCKdF1NFAsqlLr1lZt0xaMGUx0qYzyDa3B3LhfmIsGpHUujKwT-imLIyKiGOK9lPy6-HFi-TK2cnVNU1zK74LI8ZXaOq4Ysab4rtOfTvyJp3ieM58p4aODioim2ZqL3HrLrhruVprTk1slpRS_JUqwB9tTPCwr96HBsza0vLrxWht2xuv_bpyuobc6gGHwmhaEPeOAFL8gGyCVD5Wk0ivAE8LigiQyHoPEWUKK7wwAgkopeZMtp0il6_FcHAIJ-pE3UJGm5eb-y_lsQ71-BM0sz_gxEBELm3ZjZvIuRass6eko7sSNhRKYGaJndqDz5zEn_-xdQmsQjUfL0TB8OIXduvuJrp1Bs3z_4OcohEt6IZ_vC-SIjHo
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Flip+chip+package+with+improved+cap+design+and+process+for+making+thereof&rft.inventor=FARQUHAR+DONALD+S&rft.inventor=HOUSER+DAVID+E&rft.inventor=PAPATHOMAS+KONSTANTINOS+I&rft.date=2002-12-31&rft.externalDBID=B2&rft.externalDocID=US6501171B2