Integrated ESD protection circuit using a substrate triggered lateral NPN

An ESD protection circuit (100) and method is described herein. A lateral npn transistor (104) is connected between an I/O pad (110) and ground (GND). A substrate biasing circuit (150) increases the voltage across a substrate resistance (114) during an ESD event by conducting current through the sub...

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Bibliographic Details
Main Authors AMERASEKERA E. AJITH, DUVVURY CHARVAKA
Format Patent
LanguageEnglish
Published 22.10.2002
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:An ESD protection circuit (100) and method is described herein. A lateral npn transistor (104) is connected between an I/O pad (110) and ground (GND). A substrate biasing circuit (150) increases the voltage across a substrate resistance (114) during an ESD event by conducting current through the substrate. This, in turn, triggers the lateral npn (104) which clamps to voltage at the pad (110) and dissipated the ESD current. The lateral npn (104) is the primary protection device for dissipating ESD current.
Bibliography:Application Number: US19960673939