Method and device for producing undercut gate for flash memory

A method and resulting integrated circuit device (100) such as a flash memory device and resulting cell. The method includes a step of providing a substrate (115), which has an active region overlying a thin layer of dielectric material (113). The method uses a step of forming a floating gate layer...

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Bibliographic Details
Main Authors LEE RAY C, SUNG KUO-TUNG
Format Patent
LanguageEnglish
Published 22.10.2002
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A method and resulting integrated circuit device (100) such as a flash memory device and resulting cell. The method includes a step of providing a substrate (115), which has an active region overlying a thin layer of dielectric material (113). The method uses a step of forming a floating gate layer (107) overlying the thin layer of dielectric material (113), which is commonly termed a "tunnel oxide" layer, but is not limited to such a layer or material. The floating gate layer (107) has novel geometric features including slant edges (121), which extend to the dielectric material (123). The slant edges (121) create a smaller geometric area for the tunnel oxide region relative to the area between the floating gate layer and the control gate layer.
Bibliography:Application Number: US20000625143