Gradated barrier layer in integrated circuit interconnects

• Main Authors: WANG PININ CONNIE, WOO CHRISTY MEIU, MARATHE AMIT P
• Format: Patent
• Language: English
• Published: 08.10.2002
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer with an opening formed therein is formed on the semiconductor substrate. A barrier layer of barrier metal and barrier compound lines the opening, the barrier layer having a dielectric layer proximate and distal regions. The barrier layer has no barrier metal adjacent the dielectric layer proximate region and all barrier metal in the dielectric layer distal region, the barrier layer has all barrier compound adjacent the dielectric layer proximate region and no barrier compound before the dielectric layer distal region. A conductor core is over the barrier layer fills the opening and connects to the semiconductor device.