High speed DRAM local bit line sense amplifier

Disclosed is a high speed sense amplifier circuit designed for sensing data in one-transistor DRAM memory cells on bit lines within DRAM macros. The circuit utilizes a charge transfer scheme to rapidly remove charge from a small sensing first capacitor C1, generating a voltage swing delta V1, via an...

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Bibliographic Details
Main Authors DENNARD ROBERT H, KNEPPER RONALD W
Format Patent
LanguageEnglish
Published 30.07.2002
Edition7
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:Disclosed is a high speed sense amplifier circuit designed for sensing data in one-transistor DRAM memory cells on bit lines within DRAM macros. The circuit utilizes a charge transfer scheme to rapidly remove charge from a small sensing first capacitor C1, generating a voltage swing delta V1, via an FET operating in its subthreshold region by means of idling current, such transfer supplying an equal charge to the larger bit line capacitance Cb1 with small voltage swing delta Vb1. The sense amp is pre-charged to the "1" state, and senses a "0" via the charge transfer operation thusly described. A "1" is sensed when no charge transfer takes place.
Bibliography:Application Number: US20010777004