Low Resistance package for semiconductor devices

A packaging technique that significantly reduces package resistance. According to the invention, lead frames external to the package are brought in direct contact to solder balls on the surface of the silicon die inside the package molding, eliminating resistive wire interconnections. The packaging...

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Bibliographic Details
Main Authors BENCUYA IZAK, ESTACIO MARIA CHRISTINA B, SAPP STEVEN P, MALIGRO REY D, BAJE GILMORE S, TANGPUZ CONSUELO N
Format Patent
LanguageEnglish
Published 23.07.2002
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A packaging technique that significantly reduces package resistance. According to the invention, lead frames external to the package are brought in direct contact to solder balls on the surface of the silicon die inside the package molding, eliminating resistive wire interconnections. The packaging technique of the present invention is particularly suitable for power transistors.
Bibliography:Application Number: US19980141184