On-chip termination circuit

• Main Author: MOYER TODD K
• Format: Patent
• Language: English
• Published: 02.07.2002
• Edition: 7
• Subjects: BASIC ELECTRONIC CIRCUITRY; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

The present invention is an on-chip termination circuit designed to address resistance variability by making a portion of a termination resistance a MOSFET transistor operating in the triode region and replicating the termination resistance inside of a feedback loop to control the resistance of the termination resistance through the replication resistance. The MOSFET transistor's non-linear operation is mitigated by the addition of a linear resistor in series with the MOSFET transistor. By doing so, a substantial portion of the voltage across the composite termination resistance is across the linear termination resistor thereby significantly reducing the non-linear effects of the MOSFET transistor. The on-chip termination circuit includes a termination resistance, a replication resistance coupled to the termination resistance and adapted to replicate the termination resistance, and a feedback circuit adapted to maintain substantially constant a reference voltage across the replication resistance. The termination circuit further includes a voltage reference circuit adapted to generate a reference voltage and a reference current.