Flash memory process using polysilicon spacers

An EPROM cell and a method that includes a gate structure having a sidewall spacer. The sidewall spacer is made by way of an amorphous or polycrystalline silicon layer, which is converted into an insulating layer such as silicon dioxide. Deposition of the amorphous or polycrystalline silicon layer i...

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Bibliographic Details
Main Authors SU WEN-DOE, LIN LIANGN, LAI SHIHI, SUNG KUN-YU, CHANG THOMAS, TSENG MAO SONG, SUNG KUO-TUNG
Format Patent
LanguageEnglish
Published 02.04.2002
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:An EPROM cell and a method that includes a gate structure having a sidewall spacer. The sidewall spacer is made by way of an amorphous or polycrystalline silicon layer, which is converted into an insulating layer such as silicon dioxide. Deposition of the amorphous or polycrystalline silicon layer is more accurate and produces a more uniform layer than conventional dielectric layer deposition.
Bibliography:Application Number: US19980092241