Low resistance self aligned extended gate structure utilizing A T or Y shaped gate structure for high performance deep submicron FET

• Main Author: CHIU CHIHUNG
• Format: Patent
• Language: English
• Published: 04.12.2001
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

Two alternate gate electrode structures are developed with expanded top portions of the gate electrode to maintain or reduce electrode effective sheet resistance improving high frequency performance and reducing gate delay in submicron FET ULSI devices. The method for producing these structures is presented. For one structure the top surface of the expanded portion of the electrode has an essentially flat surface such as would be represented in a T shaped gate element. With the alternative structure the top surface of the expanded portion of the electrode is inclined upward from near the center of the electrode. This surface angulation results in a Y shaped gate electrode element. Both structures effectively maintain or reduce electrode sheet resistance without increasing the underlying active channel length. The process is compatible with the self aligned gate process and is also compatible with salicidation methods. It provides the conventional LDD source drain regions as well as the vertical oxide gate electrode sidewall spacers.