Method for fabricating a BiCMOS device featuring twin wells and an N type epitaxial layer

A process for fabricating a BiCMOS device, on a semiconductor substrate, featuring PFET and NFET devices, and an NPN bipolar junction transistor, has been developed. The process features the integration, or the sharing of process steps, used for both the CMOS and bipolar devices, such as the creatio...

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Bibliographic Details
Main Authors CHANG KUAN-LUN, TSUI BING-YUE
Format Patent
LanguageEnglish
Published 16.10.2001
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A process for fabricating a BiCMOS device, on a semiconductor substrate, featuring PFET and NFET devices, and an NPN bipolar junction transistor, has been developed. The process features the integration, or the sharing of process steps, used for both the CMOS and bipolar devices, such as the creation of an N type buried layer, used in one region for isolation of PFET devices, and used in a second region, of the semiconductor substrate, as a subcollector region, for the bipolar device. Features of the BiCMOS process include the formation of N well, and P well regions, for CMOS device, as well as the use of an epitaxial silicon layer, to allow optimum bipolar characteristics to be achieved.
Bibliography:Application Number: US20000534165