Adjustable PCI asynchronous clock device

Disclosed is an adjustable PCI asychronous clock device in which by using the settings of firmware after the control line is monitored and selected by using a multiplexer via an I/O port, each of the PCI slots chooses one delay unit of the time delay means, the clock signal for each kind of PCI slot...

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Bibliographic Details
Main Author YEH HENRY
Format Patent
LanguageEnglish
Published 14.08.2001
Edition7
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Disclosed is an adjustable PCI asychronous clock device in which by using the settings of firmware after the control line is monitored and selected by using a multiplexer via an I/O port, each of the PCI slots chooses one delay unit of the time delay means, the clock signal for each kind of PCI slot is delayed by the time delay means in order to regulate the clock signals of the chip set on the PCI add-on cards to be synchronous to the computer signals of the system chip set, so that the add-on cards match the PCI slots. The clock device comprises an I/O port, a plurality of multiplexers, and a time delay means.
Bibliography:Application Number: US19990248866