Method for providing ESD protection for an integrated circuit

A method for automatically generating a custom ESD network for an integrated circuit is provided. When a user provides chip size and chip capacitance for the integrated circuit, components for the customized ESD network are automatically selected based on the user-provided chip size and chip capacit...

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Bibliographic Details
Main Authors SLOAN JEFFREY H, RAHMAN TARIQ, PEQUIGNOT JAMES P, STOUT DOUGLAS W, VOLDMAN STEVEN H
Format Patent
LanguageEnglish
Published 17.07.2001
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A method for automatically generating a custom ESD network for an integrated circuit is provided. When a user provides chip size and chip capacitance for the integrated circuit, components for the customized ESD network are automatically selected based on the user-provided chip size and chip capacitance and the adequacy of the ESD behavior of an ESD network employing the selected components is evaluated.
Bibliography:Application Number: US20000657081