Method for implementing a pseudo least recent used (LRU) mechanism in a four-way cache memory within a data processing system

• Main Authors: HANLEY BRIAN PATRICK, DURHAM CHRISTOPHER MCCALL
• Format: Patent
• Language: English
• Published: 29.05.2001
• Edition: 7
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

A method for implementing a pseudo least recent used mechanism in a four-way cache memory within a data processing system is disclosed. Within a four-way set associative cache memory, each congruence class contains four cache lines. Each congruence class within the cache memory is associated to a least recently used (LRU) field that has four bits. Each of four cache lines within the congruence class is then assigned with a respective set number. The set number of a cache line designated as a least recently used set among the four cache lines is stored in two bits of the LRU field. The set number of a cache line designated as a most recently used set among the four cache lines is stored in another two bits of the LRU field. In response to a determination that the set number of the least recently used set is higher than the set number of the most recently used set, one of the remaining two cache lines that has a higher set number is assigned to be a second least recently used set.