Bit-serial neuroprocessor architecture

A neuroprocessor architecture employs a combination of bit-serial and serial-parallel techniques for implementing the neurons of the neuroprocessor. The neuroprocessor architecture includes a neural module containing a pool of neurons, a global controller, a sigmoid activation ROM look-up-table, a p...

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Bibliographic Details
Main Author TAWEL RAOUL
Format Patent
LanguageEnglish
Published 06.03.2001
Edition7
Subjects
BLASTING
CALCULATING
COMBUSTION ENGINES
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
COMPUTING
CONTROL OR REGULATING SYSTEMS IN GENERAL
CONTROLLING
CONTROLLING COMBUSTION ENGINES
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
FUNCTIONAL ELEMENTS OF SUCH SYSTEMS
HEATING
HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
LIGHTING
MEASURING
MECHANICAL ENGINEERING
MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS
PHYSICS
REGULATING
TESTING
TESTING STATIC OR DYNAMIC BALANCE OF MACHINES ORSTRUCTURES
TESTING STRUCTURES OR APPARATUS NOT OTHERWISE PROVIDED FOR
WEAPONS
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Summary:A neuroprocessor architecture employs a combination of bit-serial and serial-parallel techniques for implementing the neurons of the neuroprocessor. The neuroprocessor architecture includes a neural module containing a pool of neurons, a global controller, a sigmoid activation ROM look-up-table, a plurality of neuron state registers, and a synaptic weight RAM. The neuroprocessor reduces the number of neurons required to perform the task by time multiplexing groups of neurons from a fixed pool of neurons to achieve the successive hidden layers of a recurrent network topology.
Bibliography:Application Number: US19970956890