Method of implementing differential gate oxide thickness for flash EEPROM

Improved methods for fabricating semiconductor integrated circuit devices, in particular flash EEPROM devices. According to an embodiment, the present invention provides a method of forming a semiconductor device having a gate oxide layer (120) that is thin in some regions, such as the cell region,...

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Bibliographic Details
Main Author SUNG KUO-TUNG
Format Patent
LanguageEnglish
Published 06.02.2001
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Improved methods for fabricating semiconductor integrated circuit devices, in particular flash EEPROM devices. According to an embodiment, the present invention provides a method of forming a semiconductor device having a gate oxide layer (120) that is thin in some regions, such as the cell region, and thicker in other regions (155), such as the periphery region. The method provides the gate oxide layer with different thicknesses without the thickness control problems of prior art methods that use contaminant-containing photoresist with an etching step. According to the present invention, the gate oxide has a first thickness that is sufficiently thin to provide high driving capability for the semiconductor device, and a second thickness that is sufficiently thick to provide high voltage reliability of the semiconductor device.
Bibliography:Application Number: US19980137609