Memory system using multiple storage mechanisms to enable storage and retrieval of more than two states in a memory cell

• Main Author: WIK; THOMAS R
• Format: Patent
• Language: English
• Published: 24.10.2000
• Edition: 7
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

A memory circuit which uses multiple storage mechanisms in each of its memory cells. In one embodiment, the memory circuit includes an array of cells in which each cell has multiple storage elements. At least one of the storage elements performs its function in a different way than the rest of the storage elements. This use of multiple storage mechanisms allows for a greater freedom in memory cell design and allows for the simultaneous storage of multiple states in a single memory cell. Broadly speaking, the present invention contemplates a memory core comprising an address decoder, an array of cells, and a sense amplifier. The address decoder is configured to receive an address and responsively assert a selected word line. The array of cells includes a selected cell coupled to the selected word line, and each cell in the array of cells includes at least two storage elements. A first storage element is configured with a first state which is one of a first plurality of states, and a second storage element is configured with a second state which is one of a second, different plurality of states. The sense amplifier is coupled to the selected cell via a bit line and configured to detect the first and second states. Each cell may further include a third storage element configured with a third state which is one of a third plurality of states. In this case, the sense amplifier is also configured to detect the third state. Examples of candidate storage states include charges on a capacitance, conductivities of transistors, resistances between terminals, turn-on voltages of transistors, currents flowing in closed loops, and orientations of magnetized material.