Method for fabricating capacitor-over-bit-line dynamic random access memory (DRAM) using self-aligned contact etching technology

• Main Authors: LIAW; ING-RUEY, SUNG; JANMYE, JENG; ERIK S, CHEN; CHUN-YAO
• Format: Patent
• Language: English
• Published: 24.10.2000
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A method for making capacitor-over-bit line (COB) DRAM using a self-aligned contact etching technology is achieved. After forming FET gate electrodes, sidewall spacers are formed from a first Si3N4 etch-stop layer, while a portion of the Si3N4 is retained as an etch-stop layer on the source/drain areas. Self-aligned contact openings are etched in a first oxide layer to the source/drain areas, and polysilicon landing plugs are formed in all the self-aligned openings. A second oxide layer is deposited and contact holes are etched to the landing plugs for bit lines. A polycide layer having a cap layer is deposited and patterned to form bit lines. A third Si3N4 etch-stop layer is conformally deposited over the bit lines and patterned to form openings over the landing plugs for the capacitor node contacts while forming Si3N4 sidewall spacers on the bit lines exposed in the openings. A third oxide layer is deposited, and openings having relaxed alignment tolerances, can be etched to the capacitor node contacts because the underlying third etch-stop layer prevents overetching. A conducting layer is deposited and etched back to form bottom electrodes in the openings, and the third oxide layer is removed, while the Si3N4 etch-stop layers prevents over-etching. An interelectrode dielectric layer is deposited, and capacitor top electrodes are formed.