Method for planarizing the interface of polysilicon and silicide in a polycide structure

A method for planarizing the interface of polysilicon and silicide in a polycide structure is presented in this invention. It is by regulating the process temperature when depositing polysilicon to meanwhile improve its planarization. At first, a doped polysilicon layer is deposited on a semiconduct...

Full description

Saved in:
Bibliographic Details
Main Authors CHEN; CHIEN-HUNG, CHEN; KUANGAO, KUN-YU; SUNG, CHUNG; YI-FU
Format Patent
LanguageEnglish
Published 12.09.2000
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:A method for planarizing the interface of polysilicon and silicide in a polycide structure is presented in this invention. It is by regulating the process temperature when depositing polysilicon to meanwhile improve its planarization. At first, a doped polysilicon layer is deposited on a semiconductor substrate in the integrated circuits, then immediately after the deposition of an undoped polysilicon, the process temperature is reduced and the treatment of purging is followed with, finally, a metal silicide is formed on the undoped polysilcion.
Bibliography:Application Number: US19980121657