Method for making dynamic random access memory (DRAM) cells having zigzag-shaped stacked capacitors with increased capacitance

• Main Authors: HUANG; SEN-HUAN, CHEN; LI YEAT
• Format: Patent
• Language: English
• Published: 20.06.2000
• Edition: 7
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

DRAM cells having zigzag-shaped stacked capacitors with hemispherical gain (HSG) surfaces to increase capacitance is achieved. FET gate electrodes are formed having a planar first insulating layer thereon. Contact openings are etched for bit line contacts and capacitor node contacts. A first polysilicon layer having a top silicide layer is patterned to form bit lines and node contacts. A planar second insulating layer is formed with openings to the node contacts, which are filled with a second polysilicon to form electrical connections. A etch-stop layer is deposited followed by a multilayer composed of alternating layers of phosphosilicate and borosilicate glass. Recesses are etched in the multilayer to the node contacts, and the sidewalls in the recesses are isotropically etched to form a zigzag profile. A doped amorphous silicon layer is deposited and treated to form a HSG layer. An insulating layer is formed in the recesses to provide an etch mask and the HSG layer is etched back. The multilayer and the insulating layer are removed to provide zigzag-shaped/HSG capacitor bottom electrodes. An interelectrode dielectric layer is deposited, and a patterned fourth polysilicon layer is used to form the top electrodes to complete the array of capacitors.