Interrupt capture and hold mechanism

A processor is provided with an interrupt capture and hold mechanism. In one embodiment, a processor includes an instruction pipeline having stages for executing instructions. In the event of an exception, the instructions in the pipeline are flushed or aborted. This requires that each stage in the...

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Bibliographic Details
Main Authors GILES; CHRISTOPHER M, ECKNER; HARTVIG
Format Patent
LanguageEnglish
Published 30.05.2000
Edition7
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A processor is provided with an interrupt capture and hold mechanism. In one embodiment, a processor includes an instruction pipeline having stages for executing instructions. In the event of an exception, the instructions in the pipeline are flushed or aborted. This requires that each stage in the pipeline receive and respond to an exception-causing signal. An interrupt is an exception causing signal which may be provided by circuitry external to the processor. To ensure that such a signal is asserted long enough for each stage in the pipeline to receive and respond to it, all external hardware interrupts are routed through an interrupt capture and hold mechanism, thereby advantageously preventing the causation of an undefined processor state with little added complexity.
Bibliography:Application Number: US19980007913