Multi-speed DSP kernel and clock mechanism

The processing speed of a digital signal processor or system processor is controlled in accordance with the functions required in a task to be performed by the device, with these functions being compared to a table of maximum processing speeds at which various functions can be performed reliably by...

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Bibliographic Details
Main Authors ANDREWS; LAWRENCE P, BECKMAN; RICHARD C, PETTY, JR.; JOSEPH C, SINIBALDI; JOHN C
Format Patent
LanguageEnglish
Published 16.05.2000
Edition7
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:The processing speed of a digital signal processor or system processor is controlled in accordance with the functions required in a task to be performed by the device, with these functions being compared to a table of maximum processing speeds at which various functions can be performed reliably by the device. This method is applied to a number of digital signal processors on a communications adapter, with a core kernel of each of these digital signal processors being driven at a processing speed controlled in this way, while peripheral functions of all these digital signal processors are performed according to a clock signal synchronized with data being received from a network transmission line.
Bibliography:Application Number: US19970979530