Method and system for determining statistically based worst-case on-chip interconnect delay and crosstalk

• Main Authors: NAKAGAWA; O. SAM, OH; SOO-YOUNG, CHANG; NORMAN H, KANEVSKY; VALERY
• Format: Patent
• Language: English
• Published: 25.01.2000
• Edition: 7
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

A method and system of determining circuit performance-related characteristics, particularly delay and crosstalk, of interconnects includes defining a number of process variables which exhibit Gaussian distributions with respect to geometrical variances. A table of statistically based worst-case values representative of capacitances and resistances associated with different selections of the process variables is generated. In the preferred embodiment, the statistically based worst-case values are 3-sigma values. Also generated is a table of capacitance derivatives with respect to interconnect geometries. When a particular interconnect layout having selected process parameters is designated, the tables of 3-sigma values and derivatives are accessed to generate a resistance-capacitance (RC) net representative of the interconnect layout. The resistance and capacitance are correlated for each RC net and are partially determined by a randomized selection of values for geometries of the interconnect layout. The randomized selection of geometrical values is within the Gaussian distributions. Three-sigma delay and 3-sigma crosstalk may then be determined for the interconnect layout.