Copper-containing plug for connection of semiconductor surface with overlying conductor

• Main Authors: GARDNER; MARK I, HAUSE; FRED N
• Format: Patent
• Language: English
• Published: 21.09.1999
• Edition: 6
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

An integrated circuit fabrication process is provided in which copper is used as the contact plug material for a via. The via is a hole etched through an interlevel dielectric which is disposed upon a semiconductor topography, e.g., a silicon-based substrate having junctions therein. An inert implant may form an implant region within the semiconductor topography lying underneath the via. The process for forming the copper plug involves depositing a diffusion barrier upon the interlevel dielectric and within the via. Copper is then deposited via chemical vapor deposition upon the diffusion barrier such that the copper fills the entire via and forms a layer above the via. The copper is etched from all areas except from within the via, thereby forming a copper plug in the via. The resulting surface is then subjected to chemical-mechanical polishing before the diffusion barrier is removed from areas exclusive of the via. A conductive layer can be placed upon the interlevel dielectric and the copper plug to form a contact between the conductive layer and the semiconductor topography.