Cascoded-MOS ESD protection circuits for mixed voltage chips

Bias circuits which define control terminal voltages in a cascoded nMOS ESD protection circuit, such that the circuit is in high impedance state (OFF) during normal operation, and low impedance (ON) during an ESD event. G1 and G2 are the driver circuits which define V3 and V4 during an ESD event at...

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Bibliographic Details
Main Authors SALEM; RAOUL B, AMERASEKERA; E. AJITH
Format Patent
LanguageEnglish
Published 27.07.1999
Edition6
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Bias circuits which define control terminal voltages in a cascoded nMOS ESD protection circuit, such that the circuit is in high impedance state (OFF) during normal operation, and low impedance (ON) during an ESD event. G1 and G2 are the driver circuits which define V3 and V4 during an ESD event at the pad. During normal operation, V3 and/or V4 are high and no current flows between the pad and VSS. During an ESD event, V3 and V4 are high and both devices conduct MOS current as the lateral NPNs turn on. Diode D1 conducts current to charge Cc, the chip capacitance, raising VDD, enabling G1 and G2 to turn on and raise V3 and V4 to levels greater than the nMOS threshold voltage.
Bibliography:Application Number: US19980140051