Method for enhanced peripheral component interconnect bus split data transfer

A PC bus architecture that is compatible with an industry standard bus architecture and allows devices to transfer data more effeciently. The protocol of the present invention allows a data transaction in which a data transfer request can be made by a bus master device and then queued so that the tr...

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Bibliographic Details
Main Authors JOHNSON; LEITH L, CARLSON; RICHARD
Format Patent
LanguageEnglish
Published 27.07.1999
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A PC bus architecture that is compatible with an industry standard bus architecture and allows devices to transfer data more effeciently. The protocol of the present invention allows a data transaction in which a data transfer request can be made by a bus master device and then queued so that the transaction occurs at a later time allowing the bus to be free for other transactions until the responding device has prepared the data.
Bibliography:Application Number: US19970873348