Consistent alignment mark profiles on semiconductor wafers using PVD shadowing

Provided is a method and composition for obtaining consistent alignment mark profiles with both detectibiliy and detection accuracy for use in conjunction with CMP planarization processes in semiconductor fabrication. The method involves physical vapor deposition of metal over an angled, metal-lined...

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Bibliographic Details
Main Authors DOU; SHUMAY X, ZHAO; JOE W, CATABAY; WILBUR
Format Patent
LanguageEnglish
Published 20.07.1999
Edition6
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:Provided is a method and composition for obtaining consistent alignment mark profiles with both detectibiliy and detection accuracy for use in conjunction with CMP planarization processes in semiconductor fabrication. The method involves physical vapor deposition of metal over an angled, metal-lined alignment mark trench in the surface of a semiconductor wafer following wafer planarization by CMP. The shape of the trench creates a shadowing effect which produces minimal deposition in the angled region of the trench and overcomes asymmetric metal loss due to attack from slurry accumulating in the trench during CMP. The result is the formation of a reliable and reproducible alignment mark.
Bibliography:Application Number: US19970924902