Cache sub-array arbitration

• Main Authors: SHAH; SALIM AHMED, LIU; PEICHUN PETER, SINGH; RAJINDER PAUL
• Format: Patent
• Language: English
• Published: 18.05.1999
• Edition: 6
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

A cache sub-array arbitration circuit for receiving a plurality of address operands from a pending line of processor instructions in order to pre-fetch data needed in any memory access request in the pending instructions. The sub-array arbitration circuit compares at least two addresses correspondin...