Cache sub-array arbitration

A cache sub-array arbitration circuit for receiving a plurality of address operands from a pending line of processor instructions in order to pre-fetch data needed in any memory access request in the pending instructions. The sub-array arbitration circuit compares at least two addresses correspondin...

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Bibliographic Details
Main Authors SHAH; SALIM AHMED, LIU; PEICHUN PETER, SINGH; RAJINDER PAUL
Format Patent
LanguageEnglish
Published 18.05.1999
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A cache sub-array arbitration circuit for receiving a plurality of address operands from a pending line of processor instructions in order to pre-fetch data needed in any memory access request in the pending instructions. The sub-array arbitration circuit compares at least two addresses corresponding to memory locations in the cache, and determines in which sub-arrays the memory locations reside. If the two memory locations reside in the same sub-array, the arbitration circuit sends the higher priority address to the sub-array. If a received address operand is the real address of a cache miss, the arbitration circuit sends the cache miss address to the sub-array before other pre-fetch memory access request.
Bibliography:Application Number: US19960638661