High speed CMOS bus transmitter and receiver

• Main Authors: SANWO; IKUO JIMMY, GEORGIEF; PAUL
• Format: Patent
• Language: English
• Published: 11.05.1999
• Edition: 6
• Subjects: BASIC ELECTRONIC CIRCUITRY; CALCULATING; COMPUTING; COUNTING; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; PHYSICS; PULSE TECHNIQUE; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

A circuit, system, and method for increasing the speed of a bus by reducing the capacitive loading effect of transistors coupled to the bus are provided. The transistors, which are sub-micrometer channel length CMOS transistors, make up a tranceiver comprised of a transmitter and a reciever. The transistors that make up the transciever are coupled to the bus through a pair of Schottky diodes in series. The diode pair is coupled to isolate the bus from the junction capacitance of the transistors. The bus is a multi-segment transmission line with a characteristic impedance. The opposite ends of the transmission line are terminated with the characteristic impedance of the transmission line. The voltage swing of the bus is limited to approximately 1 volt. The pair of Schottky diodes isolate the signal bus line from the capacitive loading effects of the transistor drivers used to drive the voltages on the transmitting end of the bus, especially when the bus is being pulled to a logic high level. This results in minimal loading of the bus line and allows for a faster transmission rate. Speed is also increased by having only approximately a 1 volt swing of the bus line between logic high and logic low voltage states. All devices for this circuit can be fabricated using a standard metal-oxide-semiconductor fabrication process.