Process for forming improved cobalt silicide layer on integrated circuit structure using two capping layers

• Main Authors: YOSHIKAWA; STEPHANIE A, CATABAY; WILBUR G, WANG; ZHIHAI
• Format: Patent
• Language: English
• Published: 11.05.1999
• Edition: 6
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The formation of a cobalt silicide layer of uniform thickness over the source/drain regions and the polysilicon gate electrode of an MOS structure, which does not thin out adjacent the edges of the top surface of the polysilicon gate electrode, i.e., adjacent the oxide spacers, is achieved by first forming a titanium capping layer over a cobalt layer deposited over the MOS structure prior to formation of the cobalt silicide, and while excluding oxygen-bearing gases from the cobalt surface prior to the deposition of the titanium capping layer. Oxygen-bearing gases are then excluded from contact with the titanium capping layer prior to at least the initial annealing step to form cobalt silicide, by forming a protective titanium nitride layer over the titanium layer, either: (1) in the same chamber used to deposit the titanium layer, or (2) while still maintaining the titanium-coated semiconductor substrate in an oxygen-free atmosphere during transfer of the titanium-coated semiconductor substrate from the titanium deposition chamber to a separate titanium nitride deposition chamber. In either event, the titanium capping layer is deposited over the cobalt layer, and the protective titanium nitride layer is then formed over the titanium capping layer, prior to the first annealing step, to thereby protect the cobalt layer from oxygen-bearing gases, resulting in the formation of cobalt silicide of substantially uniform thickness over the top surface of the polysilicon gate electrode.