Method of manufacturing semiconductor device with reduced charge trapping
A semiconductor device (20) is fabricated by doping a dielectric layer (29) located over the surface of a semiconductor substrate (21). The dielectric layer (29) contains nitrogen and is doped with silicon ions by using an ion implantation process (15) such that a peak concentration (32) of the sili...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
16.03.1999
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Edition | 6 |
Subjects | |
Online Access | Get full text |
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Summary: | A semiconductor device (20) is fabricated by doping a dielectric layer (29) located over the surface of a semiconductor substrate (21). The dielectric layer (29) contains nitrogen and is doped with silicon ions by using an ion implantation process (15) such that a peak concentration (32) of the silicon ions remains in the dielectric layer (29) during the ion implantation process (15). Doping the dielectric layer (29) reduces charge trapping in the dielectric layer (29) and reduces power slump in the semiconductor device (20) during high frequency operation. |
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Bibliography: | Application Number: US19970940097 |