Method of fabricating DRAM capacitors

A method for fabricating a semiconductor device is provided comprising forming a dual silicon nitride spacer to be an etching step layer during a self-aligned contact etching step. The invention discloses a bottom electrode with a tri-forked structure and a hemispherical grain layer of a capacitor,...

Full description

Saved in:
Bibliographic Details
Main Authors JENQ; JASON, CHIEN; SUNIEH
Format Patent
LanguageEnglish
Published 23.02.1999
Edition6
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online AccessGet full text

Cover

More Information
Summary:A method for fabricating a semiconductor device is provided comprising forming a dual silicon nitride spacer to be an etching step layer during a self-aligned contact etching step. The invention discloses a bottom electrode with a tri-forked structure and a hemispherical grain layer of a capacitor, therefore the capacitor has a larger surface area. So the capacitor made by the invention has a high capacitance even though the planar surface size is reduced continually.
Bibliography:Application Number: US19980027523