Method of fabricating DRAM capacitors
A method for fabricating a semiconductor device is provided comprising forming a dual silicon nitride spacer to be an etching step layer during a self-aligned contact etching step. The invention discloses a bottom electrode with a tri-forked structure and a hemispherical grain layer of a capacitor,...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
23.02.1999
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Edition | 6 |
Subjects | |
Online Access | Get full text |
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Summary: | A method for fabricating a semiconductor device is provided comprising forming a dual silicon nitride spacer to be an etching step layer during a self-aligned contact etching step. The invention discloses a bottom electrode with a tri-forked structure and a hemispherical grain layer of a capacitor, therefore the capacitor has a larger surface area. So the capacitor made by the invention has a high capacitance even though the planar surface size is reduced continually. |
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Bibliography: | Application Number: US19980027523 |