High-performance fault tolerant computer system with clock length synchronization of loosely coupled processors

A fault-tolerant computer system employing multiple CPUs executing the same instruction stream under independent clock cycle timing. The CPUs deterministically execute the instructions internally until input or output operations require access to memory or devices which are not synchronous with the...

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Bibliographic Details
Main Authors FEY, JR.; KYRAN WILFRED, KLECKA; JAMES STEVENS, MEHTA; NIKHIL A, VRBA; RICHARD ALAN, LAMANO; LARRY LEONARD
Format Patent
LanguageEnglish
Published 01.12.1998
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A fault-tolerant computer system employing multiple CPUs executing the same instruction stream under independent clock cycle timing. The CPUs deterministically execute the instructions internally until input or output operations require access to memory or devices which are not synchronous with the local CPU clock. The CPUs are forced to take the same number of CPU clock cycles to complete the I/O operations. When the I/O operation is complete the internal processing of the instruction stream continues in a manner which is clock aligned in each of the multiple CPUs but which may be separate in real time due to oscillator drift. Accumulated drift is periodically removed by a timed interrupt which forces resynchronization of the CPUs in real time.
Bibliography:Application Number: US19960642798