Pattern generating apparatus

• Main Author: KODASHIRO; YOSHIAKI
• Format: Patent
• Language: English
• Published: 03.11.1998
• Edition: 6
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; MEASURING; MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES; PHYSICS; TESTING

In the pattern generating apparatus, various instruction codes can be generalized, so that various test patterns of different formats prepared for various testers (semiconductor test apparatus) of different models can be used in common. The pattern generating apparatus comprises: an address pointer (2) for applying a memory address (3) to an instruction memory (1); a plurality of decoders (41, 42) selected by two decode enable signals (22, 23) for generating instruction elements (5) on the basis of the instruction code (1-m) outputted by the instruction memory (1); an address generating section (6) for generating a branch destination address (7) on the basis of the instruction elements (65) outputted by the decoder (41 or 42) and for setting the generated branch destination address (7) to the address pointer (2). One of the decoders (41, 42) is selected on the basis of the decode enable signals (22, 23), and the selected decoder generates the instruction elements (5) of plural tester models. On the basis of the generated instruction elements (5), the address generating section (6) outputs the branch destination address (7) to activate the instruction memory (1) via the address pointer (2). Therefore, two patterns can be generated, separately by corresponding one of the two decoders (41, 42).