Apparatus and method to efficiently abort and restart a primary memory access

Primary memory access times are improved through an efficient technique of aborting and restarting primary memory accesses. A central processing unit of a computer includes an external cache controller to selectively generate an external cache free signal and an external cache busy signal. The centr...

Full description

Saved in:
Bibliographic Details
Main Author CHERABUDDI; RAJASEKHAR
Format Patent
LanguageEnglish
Published 27.10.1998
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:Primary memory access times are improved through an efficient technique of aborting and restarting primary memory accesses. A central processing unit of a computer includes an external cache controller to selectively generate an external cache free signal and an external cache busy signal. The central processing unit also includes a primary memory controller with an abort buffer. The primary memory controller includes circuitry to abort a primary memory access in response to the external cache busy signal. The data segment retrieved prior to aborting the primary memory access is stored in the abort buffer. The primary memory controller restarts the primary memory access in response to the external cache free signal. The restarting operation results in the data segment being passed to the external cache controller. Thereafter, the remaining data associated with the primary memory access is retrieved and sent to the external cache controller.
Bibliography:Application Number: US19960657817