Fast alignment unit for multiply-add floating point unit

• Main Authors: SCHMOOKLER; MARTIN STANLEY, OLSON; CHRISTOPHER HANS
• Format: Patent
• Language: English
• Published: 04.08.1998
• Edition: 6
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

A floating point arithmetic unit performs a multiply-add function B+(A*C) in which an alignment shifter is responsive to an input signal representative of the B mantissa. The shifter includes a sequential stack of multiplexers, typically three (3), for shifting the B mantissa to align it with the A*C product, and a complementer contained between two of the multiplexers to invert the signals when B is a negative number. A shift amount generator responsive to the A, B and C exponents produces control signals for the multiplexers. The shift amount generator includes a multiple input adder utilizing carry save adder and carry lookahead adder techniques to minimize delay, and separate decoders for each multiplexer or group of multiplexers. The generator also includes a Leading Zeros Anticipator (LZA) circuit for the most significant bits to limit shift amount signals that are within the shifting range of the shifter, which reduces the delay attributed to the carry lookahead adder. The multiplexers are arranged in a sequence such that the control signals for the first multiplexers are dependent only on the least significant bits and thus can be generated earliest, and therefore the delay of these multiplexers and the delay of the complementer is in parallel with the delay for producing the control signals to the last multiplexers.