High speed system for grey level image scaling, threshold matrix alignment and tiling, and creation of a binary half-tone image

• Main Authors: RUST; ROBERT A, FUJII; DAVID B
• Format: Patent
• Language: English
• Published: 23.06.1998
• Edition: 6
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; IMAGE DATA PROCESSING OR GENERATION, IN GENERAL; PHYSICS; PICTORIAL COMMUNICATION, e.g. TELEVISION

A system converts a source image of grey level pixel values into a destination image of binary pixel values, the source and destination images having different levels of resolution. The system includes a memory which stores at least a portion of a row of source pixels, a corresponding row of a grey level threshold matrix and a relative input index array (RIIA) which employs a single index bit for each column of the destination image. Index bits are read from the memory and placed in an index bit register, and N source pixel values are written into a source register. A scale logic circuit includes N destination image column outputs and is responsive to each index bit, to output one grey level source pixel on each output. An alignment switch is responsive to a clock input to provide N threshold pixel value outputs that are aligned with corresponding destination image pixels. A comparator compares each source grey level pixel with a corresponding threshold pixel value and assigns a binary value in accordance with the comparison action. A controller initially loads the registers with values from the memory and then synchronously operates the system to output, in parallel, N destination image binary pixel values per clock cycle.