Memory devices having a flexible redundant block architecture
A memory device includes a plurality of data input/output (I/O) lines and means for receiving a column address. The memory device also includes a plurality of primary memory cells, a selected primary memory cell of the plurality of primary memory cells being connected to a primary global I/O line in...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
02.06.1998
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Edition | 6 |
Subjects | |
Online Access | Get full text |
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Summary: | A memory device includes a plurality of data input/output (I/O) lines and means for receiving a column address. The memory device also includes a plurality of primary memory cells, a selected primary memory cell of the plurality of primary memory cells being connected to a primary global I/O line in response to receipt of one column address, and a plurality of redundant memory cells, a selected redundant memory cell of the plurality of redundant memory cells being connected to a redundant global I/O line in response to receipt of the one column address. One of the primary global I/O line and the redundant global I/O line are selectively connected to one of the plurality of data I/O lines such that one of the selected primary memory cell and the selected redundant memory cell is connected to the one data I/O line to thereby enable data transfer therebetween, preferably by enabling one of a primary I/O sense amplifier and a redundant I/O sense amplifier connected to the primary and redundant global I/O lines, respectively. |
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Bibliography: | Application Number: US19960754673 |