Circuit and method to externally adjust internal circuit timing
A circuit and method of using a test mode to control the timing of an internal signal using an external control in an integrated circuit. The test mode is designed such that the timing of the internal signal is derived from the external control which can be arbitrarily controlled by a tester. The ex...
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Main Authors | , , |
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Format | Patent |
Language | English |
Published |
28.04.1998
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Edition | 6 |
Subjects | |
Online Access | Get full text |
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Summary: | A circuit and method of using a test mode to control the timing of an internal signal using an external control in an integrated circuit. The test mode is designed such that the timing of the internal signal is derived from the external control which can be arbitrarily controlled by a tester. The external signal can be applied to an existing pin for chip control, provided that there is no conflict between the test mode and the operation of the integrated circuit. |
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Bibliography: | Application Number: US19960777559 |