High speed programmable logic architecture

Architecture for a programmable logic device is described which can operate at substantially faster clock rates than present programmable logic devices. Instead of employing passive circuit elements to interconnect the programmable logic elements and the input and output data buses, controllable act...

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Bibliographic Details
Main Author SASAKI; PAUL T
Format Patent
LanguageEnglish
Published 21.04.1998
Edition6
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Summary:Architecture for a programmable logic device is described which can operate at substantially faster clock rates than present programmable logic devices. Instead of employing passive circuit elements to interconnect the programmable logic elements and the input and output data buses, controllable active driver circuits are employed. These circuits eliminate essentially all of the resistance present in prior art passive connections.
Bibliography:Application Number: US19950580668