Self-timed multiplier array

Logic circuitry implemented in a pipeline manner receives a request signal along with received data into the pipeline and proceeds to insure that each successive stage within the pipeline is placed into a standby state and out of a precharge state previous to the arrival of the data wave into each o...

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Bibliographic Details
Main Author KLIM; PETER JUERGEN
Format Patent
LanguageEnglish
Published 14.04.1998
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Logic circuitry implemented in a pipeline manner receives a request signal along with received data into the pipeline and proceeds to insure that each successive stage within the pipeline is placed into a standby state and out of a precharge state previous to the arrival of the data wave into each of the successive stages. The circuitry also resets each of the stages after a stage has evaluated the data. The logic circuitry may be employed within a multiplier array in a processor.
Bibliography:Application Number: US19950515335