Method and circuit for reducing offset voltages for a differential input stage

• Main Authors: GRIFFITH; RICHARD S, DOTSON; ROBERT N, PETTY; THOMAS D, VYNE; ROBERT L
• Format: Patent
• Language: English
• Published: 10.03.1998
• Edition: 6
• Subjects: AMPLIFIERS; BASIC ELECTRONIC CIRCUITRY; ELECTRICITY; PULSE TECHNIQUE

A trim circuit (10) and method of reducing offset voltages in a differential input stage. The differential input transistors (32 and 42) have separate bulk terminals for receiving a voltage to compensate for the input offset voltage. A current source (60) supplies a static current to the offset compensation circuit for generating a bias voltage at node (55). The transistors (64 and 66) receive a voltage at input terminals (30 and 40) and supply an additional current to an offset compensation circuit (20). A switch circuit (50) has switch pairs (52, 56, and 54, 58) for transferring a voltage to the bulk terminal of one of the differential transistors (32 and 42) while grounding the bulk terminal of the other transistor. The differential voltage supplied across the bulk terminals of transistors (32 and 42) changes the threshold voltage of the transistors reducing the offset voltage of the input stage.